This invention relates to a semiconductor integrated circuit device (LSI) and, more particularly, to a mode of adjustment of the impedance of a pad for connecting a signal wiring on an LSI chip to an external pin.
Impedances of input/output pins of LSIs are determined by capacitances and resistances of wirings outside their packages, lead frames, gold bonding, pads on the LSI chips and signal wirings connected to the pads. Impedances determine propagation speeds, noises, waveform distortions, and so on, of input signals. In terms of the signal speed, capacitance and resistance had better be small. However, certain capacitance and resistance are required from the viewpoint of countermeasures against noises. Therefore, capacity and resistance of an input/output pin are designed to realize users"" desired input/output characteristics, taking these requirements into consideration. Pads on LSI chips and signal wirings connected thereto are portions permitting ample freedom for adjustment of capacitance and resistance of input/output pins. However, as LSIs are large-scaled while miniaturizing their elements and wirings and increasing their density, adjustment of impedances of pads and signal wirings on LSIs are getting difficult.
This is explained below by way of a specific example. FIG. 13 shows a layout of a DRAM chip. The DRAM chip 1 has formed four divisional memory cell blocks 2, for example, as illustrated. Each memory cell block 2 includes a column decoder 3 and a row decoder 4 along inner edges thereof. The region between right and left memory cell blocks 2 is used to locate a peripheral circuit formed in region 7. The region between upper and lower memory cell blocks 2 is used to locate a peripheral circuit formed in region 5, and it is also used to make bus lines 8 such as address bus, data bus, and so forth, and pads 6 for externally drawing signal lines as shown in FIG. 14 in an enlarged scale.
In the LSI where bus lines 8 are closely packed near the alignment of pads 6, it is difficult to adjust impedance of a single pad 6 without affecting a signal wiring connected to another pad.
Assume here, for example, that when it is desired to add a capacity to a certain single pad 6, a capacitor 9 connected to a signal line 8a extending to a certain pad 6 is provided as shown in FIG. 15. The capacitor 9 is buried, for example, under signal lines 8a through 8c to electrically isolate it via an insulation film in order not to prevent signals from travelling in adjacent signal lines 8b and 8c. Nevertheless, capacitance coupling still occurs between signal lines 8b, 8c adjacent to the signal line 8a and the capacitor 9, and capacitance inevitably increases in the signal lines 8b and 8c. 
Also, assume that a resistor-forming conductor 10 bent as shown in FIG. 16, for example, is provided to insert a resistor between the pad 6 and the signal line 8a connected thereto. Here again, useless capacitance coupling inevitably occurs respectively between it and other signal lines 8b, 8c located nearby. Usually, a high-density LSI, as referred to above, does not have an ample space for making such a resistor-forming conductor 10. If such a resistor-forming conductor 10 is nevertheless made there, other signal wirings in a common layer cannot be extended in that portion. That is, the adjusting mode as shown in FIG. 16 needs an essential change in layout of elements and wirings.
As explained above, it has been difficult to adjust impedance of a certain pad in a high-density LSI chip without affecting impedances and positions of other pads and signal lines or without changing the basic design of layout.
It is therefore an object of the invention to provide a semiconductor integrated circuit device enabling adjustment of the impedance of a certain pad without affecting characteristics and locations of other pads and signal wirings and without inviting a design change in essential layout.
According to the invention, there is provided a semiconductor integrated circuit device including semiconductor elements, signal wirings and pads formed on a semiconductor substrate so as to connect particular one of the semiconductor elements to particular one of the signal wirings and connect the particular signal wiring to particular one of the pads, comprising:
a capacitor-forming conductor made in a top layer to surround the particular pad and connected to the particular pad; and
a first capacitance coupling conductor made in the top layer between the particular pad and the capacitor-forming conductor and brought into capacitance coupling with the particular pad and the capacitor-forming conductor, respectively.
According to the invention, there is further provided a semiconductor integrated circuit device comprising:
semiconductor elements, signal wirings and pads formed on a semiconductor substrate so as to connect particular one of the semiconductor elements to particular one of the signal wirings and connect the particular signal wiring to particular one of the pads; and
a resistor-forming conductor connected between the particular signal wiring and the particular pad.
According to the invention, there is further provided a semiconductor integrated circuit device comprising:
semiconductor elements, signal wirings and pads formed on a semiconductor substrate so as to connect particular one of the semiconductor elements to particular one of the signal wirings and connect the particular signal wiring to particular one of the pads;
a fist capacitance-coupling conductor made under the particular pad via an insulation film;
a capacitor-forming conductor made under the capacitance-coupling conductor via an insulation film and connected to the particular pad; and
a second capacitance-coupling conductor made under the capacitor-forming conductor via an insulation film and connected to the first capacitance-coupling conductor.
According to the invention, there is further provided a semiconductor integrated circuit device having formed on a semiconductor substrate a plurality of elements, signal wirings connecting these elements, and a plurality of pads for connecting desired one or more of the signal wirings to one or more external pins, comprising:
at least one impedance adjusting conductor pattern made to surround particular one of the pads and connected to the particular pad.
The impedance adjusting conductor pattern may be a capacitor-forming conductor, and a source line conductor may be made to encircle the capacitor-forming conductor and get into capacitance coupling with the capacitor-forming conductor and the pad.